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Part Number PPC405CR Revision 1.02 - January 11, 2005
PPC405CR
Features
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Data Sheet
PowerPC 405CR Embedded Processor
PowerPC(R) 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Multiply-Accumulate (MAC) function, including fast multiply unit - Programmable Timers Synchronous DRAM (SDRAM) interface operating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications External Peripheral Bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported * DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels Programmable Interrupt Controller supports interrupts from a variety of sources - Supports 7 external and 10 internal interrupts - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core - Programmable critical interrupt priority ordering Two serial ports (16550 compatible UART) One IIC interface General Purpose I/O (GPIO) available Supports JTAG for board level testing Internal Processor Local Bus (PLB) runs at SDRAM interface frequency
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Description
The PowerPC 405CR (PPC405CR) is a 32-bit RISC embedded controller. High performance, peripheral integration, and low cost make the device ideal for wired communications, network printers, and other computing applications. This device is an easy upgrade for systems based on PowerPC 403xx embedded processors, while providing a base for custom chip designs. The controller is powered by a PPC405 embedded core. This core tightly couples a 266 MHz CPU, MMU, instruction and data caches, and debug logic. Finetuning of the core reduces data transfer overhead, minimizes pipeline stalls, and improves performance. The PPC405CR employs the IBM CoreConnectTM bus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 133-MHz Processor Local Bus (PLB) and a 32-bit, 66-MHz On-Chip Peripheral Bus (OPB). High-performance peripherals attach to the PLB and less performance-critical peripherals attach to the OPB. Technology: CMOS SA-12E 0.25 m (0.18 m Leff) Package: 27 mm, 316-ball enhanced plastic ball grid array (E-PBGA) Power (estimated): Typical 0.8 W, Maximum 2.0 W at 200MHz.
AMCC
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intialization Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 21 22 22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
List of Figures
Figure 1. PPC405CR Embedded Controller Functional Block Diagram .................................................................. 5 Figure 2. 27mm, 316-Ball E-PBGA Package ......................................................................................................... 10 Figure 3. Package Thermal Specifications ............................................................................................................ 28 Figure 4. 5V-Tolerant I/O Input Current ................................................................................................................. 30 Figure 5. Timing Waveform .................................................................................................................................... 32 Figure 6. Input Setup and Hold Waveform ............................................................................................................. 35 Figure 7. Output Delay and Float Timing Waveform .............................................................................................. 35
List of Tables
Table 1. System Memory Address Map 4GB System Memory ................................................................................ 6 Table 2. DCR Address Map 4KB Device Configuration Register ............................................................................. 6 Table 3. Signals Listed Alphabetically ................................................................................................................... 11 Table 4. Signals Listed by Ball Assignment ........................................................................................................... 18 Table 5. Pin Summary ........................................................................................................................................... 21 Table 6. Signal Functional Description .................................................................................................................. 23 Table 7. Absolute Maximum Ratings ..................................................................................................................... 28 Table 8. Recommended DC Operating Conditions ................................................................................................ 29 Table 9. Input Capacitance .................................................................................................................................... 30 Table 10. Clocking Specifications .......................................................................................................................... 32 Table 11. Peripheral Interface Clock Timings ........................................................................................................ 34 Table 12. I/O Specifications--All speeds ............................................................................................................... 36 Table 13. I/O Specifications--133 and 200MHz .................................................................................................... 37 Table 14. I/O Specifications--266MHz .................................................................................................................. 38 Table 15. Strapping Pin Assignments .................................................................................................................... 39
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Ordering, PVR, and JTAG Information
Product Name PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR PPC405CR Order Part Number1, 2 PPC405CR-3BC133C PPC405CR-3BC133CZ PPC405CR-3KC133C PPC405CR-3KC133CZ PPC405CR-3BC200C PPC405CR-3BC200CZ PPC405CR-3KC200C PPC405CR-3KC200CZ PPC405CR-3BC266C PPC405CR-3BC266CZ PPC405CR-3KC266C PPC405CR-3KC266CZ Processor Frequency 133MHz 133MHz 133MHz 133MHz 200MHz 200MHz 200MHz 200MHz 266MHz 266MHz 266MHz 266MHz Package 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA 27mm, 316 ball E-PBGA Rev Level C C C C C C C C C C C C PVR Value 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 JTAG ID 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049 0x42051049
Notes: 1. Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. 2. Package type B contains lead; package type K is lead-free.
This section provides the part numbering nomenclature for the PPC405CR. For availability, contact your local AMCC sales office. Each part number contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PPC405CR Embedded Processor User's Manual for details on the register content. Part Number Key
PPC405CR-3BC266Cx
Part Number Grade 3 Reliability
Shipping Package Blank = Tray Z = Tape and reel Operational Case Temperature Range (-40C to +85C) Processor Speed 133MHz 200MHz 266MHz Revision Level
Package (E-PBGA)
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AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Figure 1. PPC405CR Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers MMU PPC405 Processor Core JTAG 8KB D-Cache DCU Trace ICU 16KB I-Cache Arb On-chip Peripheral Bus (OPB) DMA Controller (4-Channel) Arb Code Decompression (CodePackTM) External Bus Controller External Bus Master Controller Processor Local Bus (PLB) GPIO IIC UART UART Power Mgmt DCRs
DCR Bus
OPB Bridge
SDRAM Controller
13-bit addr 32-bit data
32-bit addr 32-bit data
The PPC405CR is designed using the IBM Microelectronics Blue Logic(R) methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Address Map Support
The PPC405CR incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405CR processor through the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (4GB System Memory)
Function General Use Boot-up Subfunction SDRAM and External Peripherals Note: Any of the address ranges listed at right may be use for any of the above functions. Peripheral Bus Boot 1 UART0 UART1 Internal Peripherals IIC0 OPB Arbiter GPIO Controller Registers Start Address 0x00000000 0xF0000000 0xFFE00000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 End Address 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F Size 3830MB 256MB 2MB 8B 8B 32B 64B 128B
Notes: 1. When peripheral bus boot is selected, Peripheral bank 0 is automatically configured at reset to the address range listed above. 2. After the boot process, software may reassign the boot memory region for other uses. 3. All address ranges not listed above are reserved.
Table 2. DCR Address Map
Function Total DCR Address Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved PLB Registers Reserved OPB Bridge Out Registers Reserved Clock, Control, and Reset Power Management Interrupt Controller Reserved DMA Controller Registers Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB). Space1 Start Address 0x000 0x000 0x010 0x012 0x014 0x016 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0D0 0x100 0x140 End Address 0x3FF 0x00F 0x011 0x013 0x015 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B7 0x0BF 0x0CF 0x0FF 0x13F 0x3FF Size 1KW (4KB)1 16W 2W 2W 2W 106W 16W 16W 8W 8W 8W 8W 16W 48W 64W 704W
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
SDRAM Memory Controller
The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four logical banks. Up to 256MB per bank are supported, up to a maximum of 1 GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: * * * * * * * * * * 11x8 to 13x11 addressing for SDRAM (2- and 4-bank) 32-bit memory interface support Programmable address compare for each bank of memory Industry standard 168-pin DIMMS are supported (some configurations) 4MB to 256MB per bank Programmable address mapping and timing Auto refresh Page mode accesses with up to 4 open pages Power Management (self-refresh) Error Checking and Correction (ECC) support - Standard SEC/DED coverage - Aligned nibble error detect - Address error logging
External Peripheral Bus Controller (EBC)
* * * * * * Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripheral I/O Up to 66MHz operation Burst and non-burst devices 8-, 16-, 32-bit byte-addressable data bus width support Programmable 2K clock time-out counter with disable for Ready Programmable access timing per device - 0-255 wait states for non-burst devices - 0-31 burst wait states for first access and up to 7 wait states for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS Programmable address mapping Peripheral device pacing with external "Ready" External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control
* * *
DMA Controller
* Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
* * * * * * * * *
- Buffered memory to peripheral transfers Four channels Scatter/Gather capability for programming multiple DMA operations 8-, 16-, 32-bit peripheral support (OPB and external) 32-bit addressing Address increment or decrement Internal 32-byte data buffering capability Supports internal and external peripherals Support for memory mapped peripherals Support for peripherals running on slower frequency buses
UART
* * * * * * * One 8-pin UART and one 4-pin UART interface provided Selectable internal or external serial clock to allow wide range of baud rates Register compatibility with NS16550 register set Complete status reporting capability Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode Fully programmable serial-interface characteristics Supports DMA using internal DMA engine
IIC Bus Interface
* * * * * * * * * * * * * Compliant with Phillips(R) Semiconductors I2C Specification, dated 1995 Operation at 100kHz or 400kHz 8-bit data 10- or 7-bit address Slave transmitter and receiver Master transmitter and receiver Multiple bus masters Supports fixed VDD IIC interface Two independent 4 x 1 byte data buffers Twelve memory-mapped, fully programmable configuration registers One programmable interrupt request signal Provides full management of all IIC bus protocol Programmable error recovery
General Purpose IO (GPIO) Controller
* * Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses. All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with: - 7 of 8 chip selects. - All seven external interrupts. - All nine instruction trace pins. Each GPIO output is separately programmable to emulate an open-drain driver (two states, drive to zero or open circuit).
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: * * * * * * Supports 7 external and 10 internal interrupts Edge triggered or level-sensitive Positive or negative active Non-critical or critical interrupt to PPC405 processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector for faster vector processing
JTAG
* * * IEEE 1149.1 test access port IBM RISCWatch debugger support JTAG Boundary Scan Description Language (BSDL)
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Figure 2. 27mm, 316-Ball E-PBGA Package
Top View
Gold Gate Release Corresponds to A1 Ball Location
Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded
15.0 TYP 7.5 TYP
27.0 REF
27.0
Notes: 1. All dimensions are in mm.
2. Package available in leaded and lead-free configurations.
C 0.20 C
0.20
Bottom View
27.0 24.13
A
0.25 C 0.35 C
27.0
Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6
1.27 TYP Mold Compound
Thermal Balls PCB Substrate
B
7
8
9
11 13 15 17 19 10 12 14 16 18 20
0.6 0.1 2.65 MAX
0.75 0.15 SOLDERBALL x 316 0.30 M C A B 0.15 M C
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AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Pin Lists
In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. The page number listed gives the page in "Signal Functional Description" on page 23 where the signals in the indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 7)
Signal Name AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 BusReq CAS ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB DrvrInh1 DrvrInh2 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOT0/TC0 EOT1/TC1 EOT2/TC2 EOT3/TC3 ExtAck ExtReq ExtReset Ball E20 J17 H18 L19 N17 P17 U19 P2 K17 J19 G20 C16 B17 B16 A14 A19 C15 B15 A8 U18 W14 Y10 U8 V19 F17 C19 V17 Y18 U14 V13 Y13 V12 W11 V11 G4 F2 W1 Y2 U5 Y3 P4 Power SDRAM Interface Group Page 27 23
SDRAM
23
External Master Peripheral SDRAM SDRAM
25 23 23
External Slave Peripheral
23
External Slave Peripheral
23
SDRAM
23
SDRAM System
23 26
SDRAM
23
External Slave Peripheral
23
External Master Peripheral
25
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 2 of 7)
Signal Name Ball A1 A6 A10 A15 A20 B2 B19 C3 C18 D4 D17 E5 E10 E11 E16 F1 F20 J9 J10 J11 J12 K5 K9 K10 K11 K12 K16 K20 L1 L5 L9 L10 L11 L12 L16 M9 M10 M11 M12 R1 R20 T5 T10 T11 T16 U4 U17 V3 V18 W2 W19 Y1 Y6 Y11 Y15 Y20 Interface Group Page
GND
Power Note: J9-J12, K9-K12, L9-L12, and M9-M12 are also thermal balls.
27
GND (cont)
Power
27
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AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 3 of 7)
Signal Name GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] Halt HoldAck HoldPri HoldReq IICSCL IICSDA IRQ0[GPIO17] IRQ1[GPIO18] IRQ2[GPIO19] IRQ3[GPIO20] IRQ4[GPIO21] IRQ5[GPIO22] IRQ6[GPIO23] MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 Ball B18 D16 C17 P18 T17 W18 Y19 W13 V6 E19 T4 T3 V2 U15 W17 D18 C20 E18 D20 G17 F18 W20 Y7 W7 V8 U7 Y4 U6 W4 V5 W3 V4 U3 V1 T2 H20 G18 Interface Group Page
System
26
System External Master Peripheral Internal Peripheral Internal Peripheral
26 25 25 25
Interrupts
26
SDRAM Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on this bus.
23
SDRAM
23
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 4 of 7)
Signal Name MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball J18 K19 L20 M20 M19 L18 L17 N20 N19 M18 M17 P20 P19 N18 U20 T18 W16 Y17 Y16 V14 Y14 U12 W12 Y12 Y9 W9 V10 U10 Y8 W8 V9 U9 F5 G5 P5 R5 T6 T7 T14 T15 F16 G16 P16 R16 E6 E7 E14 E15 Interface Group Page
SDRAM Note: MemData0 is the most significant bit (msb) on this bus.
23
OVDD
Power
27
14
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 7)
Signal Name PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1[GPIO10] PerCS2[GPIO11] PerCS3[GPIO12] PerCS4[GPIO13] PerCS5[GPIO14] PerCS6[GPIO15] PerCS7[GPIO16] Ball A3 A4 B6 D7 C6 B7 D8 C7 B8 A7 D9 C8 B9 D10 C9 A9 B11 A11 B12 D11 A13 B13 C12 D12 B14 C13 D13 A16 C14 D14 A17 D15 E2 D3 D6 B5 C5 A5 B10 C10 A12 C11 Interface Group Page
External Slave Peripheral Note: PerAddr0 is the most significant bit (msb) on this bus.
23
External Slave Peripheral External Master Peripheral
23 25
External Slave Peripheral
23
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 7)
Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWE RAS RcvrInh Ball U2 R4 U1 R2 R3 T1 N4 P3 N2 P1 M4 N3 M2 N1 L4 M3 L2 M1 K2 L3 K1 J1 J2 K3 K4 H1 H2 J3 J4 G1 G2 H3 B1 E4 C2 G3 E1 H4 E3 C1 D2 F4 F3 D1 C4 K18 E17 J20 G19 R17 T20 V16 Interface Group Page
External Slave Peripheral Note: PerData0 is the most significant bit (msb) on this bus.
23
External Master Peripheral External Slave Peripheral
25 23
External Slave Peripheral
23
External Slave Peripheral External Slave Peripheral
23 23
External Slave Peripheral
23
External Slave Peripheral SDRAM System Other pins Notes: 1. Connect G19 to ground. 2. Other reserved pins are not connected internally within the chip and should not have signals, voltage, or ground applied to them.
23 23 26
Reserved
27
16
AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 7)
Signal Name SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk TMS TRST UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_DSR[UART1_CTS] UART1_RTS[UART1_DTR] UART1_Rx UART1_Tx UARTSerClk Ball H17 A18 D19 B4 A2 D5 F19 B20 B3 H19 W10 R18 U16 U13 V15 V20 T19 W15 V7 W6 W5 Y5 R19 E8 E9 E12 E13 H5 H16 J5 J16 M5 M16 N5 N16 T8 T9 T12 T13 U11 System Interface Group Page 26
JTAG System System JTAG JTAG
26 26 26 26 26
Internal Peripheral
25
Internal Peripheral
25
Internal Peripheral
25
VDD
Power
27
WE
SDRAM
23
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Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 1 of 3)
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 GND TDI PerAddr0 PerAddr1 PerCS3[GPIO12] Gnd PerAddr9 DMAReq3 PerAddr15 GND PerAddr17 PerCS6[GPIO15] PerAddr20 DMAAck3 GND PerAddr27 PerAddr30 SysErr DMAReq0 GND PerErr GND TMS TCK PerCS1[GPIO10] PerAddr2 PerAddr5 PerAddr8 PerAddr12 Signal Name Ball B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Signal Name PerCS4[GPIO13] PerAddr16 PerAddr18 PerAddr21 PerAddr24 DMAReq2 DMAAck2 DMAAck1 GPIO1[TS1E] GND TmrClk PerR/W PerPar0 GND PerWE PerCS2[GPIO11] PerAddr4 PerAddr7 PerAddr11 PerAddr14 PerCS5[GPIO14] PerCS7[GPIO16] PerAddr22 PerAddr25 PerAddr28 DMAReq1 DMAAck0 GPIO3[TS1O] GND Ball C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 Signal Name DrvrInh2 IRQ1[GPIO18] PerWBE3 PerWBE0 PerClk GND TDO PerCS0 PerAddr3 PerAddr6 PerAddr10 PerAddr13 PerAddr19 PerAddr23 PerAdd26 PerAddr29 PerAddr31 GPIO2[TS2E] GND IRQ0[GPIO17] SysReset IRQ3[GPIO20] PerPar2 PerBLast PerReady PerOE GND OVDD OVDD Ball E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G16 VDD VDD GND GND VDD VDD OVDD OVDD GND Rcrvinh IRQ2[GPIO19] Halt AVDD GND EOT1/TC1 PerWBE2 PerWBE1 OVDD OVDD DrvrInh1 IRQ5[GPIO22] TestEn GND PerData29 PerData30 PerPar1 EOT0/TC0 OVDD OVDD Signal Name
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Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 3)
Ball G17 G18 G19 G20 H1 H2 H3 H4 H5 H16 H17 H18 H19 H20 J1 J2 J3 J4 J5 J9 J10 J11 J12 J16 J17 J18 J19 J20 K1 Signal Name IRQ4[GPIO21] MemClkOut1 Reserved ClkEn1 PerData25 PerData26 PerData31 PerPar3 VDD VDD SysClk BA1 TRST MemClkOut0 PerData21 PerData22 PerData27 PerData28 VDD Thermal Ball Thermal Ball Thermal Ball Thermal Ball VDD BA0 MemData0 ClkEn0 Reserved PerData20 Ball K2 K3 K4 K5 K9 K10 K11 K12 K16 K17 K18 K19 K20 L1 L2 L3 L4 L5 L9 L10 L11 L12 L16 L17 L18 L19 L20 M1 M2 Signal Name PerData18 PerData23 PerData24 GND Thermal Ball Thermal Ball Thermal Ball Thermal Ball GND CAS RAS MemData1 GND GND PerData16 PerData19 PerData14 GND Thermal Ball Thermal Ball Thermal Ball Thermal Ball GND MemData6 MemData5 BankSel0 MemData2 PerData17 PerData12 Ball M3 M4 M5 M9 M10 M11 M12 M16 M17 M18 M19 M20 N1 N2 N3 N4 N5 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P16 P17 Signal Name PerData15 PerData10 VDD Thermal Ball Thermal Ball Thermal Ball Thermal Ball VDD MemData10 MemData9 MemData4 MemData3 PerData13 PerData8 PerData11 PerData6 VDD VDD BankSel1 MemData13 MemData8 MemData7 PerData9 BusReq PerData7 ExtReset OVDD OVDD BankSel2 Ball P18 P19 P20 R1 R2 R3 R4 R5 R16 R17 R18 R19 R20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Signal Name GPIO4[TS2O] MemData12 MemData11 GND PerData3 PerData4 PerData1 OVDD OVDD Reserved UART0_DCD UARTSerClk GND PerData5 MemAddr12 HoldPri HoldAck GND OVDD OVDD VDD VDD GND GND VDD VDD OVDD OVDD GND
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Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 3)
Ball T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name GPIO5[TS3] MemData15 UART0_RX Reserved PerData2 PerData0 MemAddr10 GND ExtAck MemAddr5 MemAddr3 DQM3 MemData31 MemData27 WE MemData21 UART0_DTR ECC2 IICSCL UART0_DSR GND Ball U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Signal Name DQM0 BankSel3 MemData14 MemAddr11 HoldReq GND MemAddr9 MemAddr7 GPIO9[TrcClk] UART1_DSR [UART1_CTS] MemAddr2 MemData30 MemData26 ECC7 ECC5 ECC3 MemData19 UART0_RI Reserved ECC0 GND Ball V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Signal Name DQMCB UART0_RTS EOT2/TC2 GND MemAddr8 MemAddr6 UART1_RX UART1_RTS [UART1_DTR] MemAddr1 MemData29 MemData25 UART0_CTS ECC6 MemData22 GPIO8[TS6] DQM1 UART0_TX MemData16 IICSDA GPIO6[TS4] GND Ball W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name IRQ6[GPIO23] GND EOT3/TC3 ExtReq MemAddr4 UART1_TX GND MemAddr0 MemData28 MemData24 DQM2 GND MemData23 ECC4 MemData20 GND MemData18 MemData17 ECC1 GPIO7[TS5] GND
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Data Sheet
Signal Descriptions
The PPC405CR embedded controller is packaged in a 316-ball enhanced plastic ball grid array (E-PBGA). The following table provides a summary of the number of package pins associated with each functional interface group. Table 5. Pin Summary
Group
SDRAM External Peripheral External Master Internal Peripheral Interrupts JTAG System Total Signal Pins AVDD OVDD VDD Gnd Thermal (and Gnd) Reserved Total Pins
No. of Pins
71 97 9 15 7 5 18 222 1 16 16 40 16 5 316
Multiplexed Pins In the table "Signal Functional Description" on page 23, each I/O signal is listed along with a short description of the signal function. Some signals are multiplexed onto the same package pin (ball) so that the pin can be used for different functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address pins are used as outputs by the PPC405CR to broadcast an address to external slave devices when the PPC405CR has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405CR. Intialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Strapping" on page 39). Note that these are not multiplexed pins since the function of the pins is not programmable. Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V (10k to +5V can be used on 5V tolerant I/Os) and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor.
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Data Sheet
If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405CR. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405CR requires only the pullup and pull-down terminations as specified in the "Signal Functional Description" on page 23, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral and SDRAM buses should be configured and terminated as follows: * * Peripheral interface--PerAddr0:31, PerData0:31, and all of the control signals are driven by default. Terminate PerReady high and PerError low. SDRAM--Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405CR to actively drive all of the SDRAM address, data, and control signals.
External Bus Control Signals All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405CR Embedded Processor User's Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions and/or when an external master owns the peripheral bus. As a result, a pullup resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405CR. Please refer to "Signals Listed Alphabetically" on page 11 for the pin number to which each signal is assigned.
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Data Sheet
Table 6. Signal Functional Description (Sheet 1 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See "External Bus Control Signals" on page 22.
Signal Name Description I/O Type
Notes
SDRAM Interface
Memory Data bus. Notes: 1. MemData0 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory Address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr0 is the least significant bit (lsb). Bank Address supporting up to four internal banks. Row Address Strobe. Column Address Strobe. DQM for byte lanes 0 (MemData0:7), 1 (MemData8:15), 2 (MemData16:23), and 3 (MemData24:31). DQM for ECC check bits. ECC check bits 0:7. Select up to four external SDRAM banks. Write Enable. SDRAM Clock Enable. Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer.
MemData0:31
I/O
3.3V LVTTL
MemAddr12:0
O
3.3V LVTTL
BA0:1 RAS CAS DQM0:3 DQMCB ECC0:7 BankSel0:3 WE ClkEn0:1 MemClkOut0:1
O O O O O I/O O O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External Slave Peripheral Interface
PerData0:31 Peripheral data bus used by PPC405CR when not in external master mode, otherwise used by external master. Note: PerData0 is the most significant bit (msb) on this bus. Peripheral address bus used by PPC405CR when not in external master mode, otherwise used by external master. Note: PerAddr0 is the most significant bit (msb) on this bus. Peripheral byte parity signals. As outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. As outputs, pins are used by either peripheral controller or the DMA controller depending upon the type of transfer involved. Used as inputs when external bus master owns the external interface. Peripheral write enable. Active when any of the four PerWBE0:3 signals are active. I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
PerAddr0:31
I/O
1
PerPar0:3
I/O
1
PerWBE0:3
I/O
5V tolerant 3.3V LVTTL
1, 7
PerWE
O
5V tolerant 3.3V LVTTL
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Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See "External Bus Control Signals" on page 22.
Signal Name PerCS0 Description Peripheral chip select bank 0. Seven additional peripheral chip selects or General Purpose I/O. To access this function, software must toggle a DCR register bit. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC405CR is the bus master, it enables the selected device to drive the bus. Used by the PPC405CR when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise it used by the external master as an input to indicate the direction of transfer. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC405CR when not in external master mode, otherwise used by external master. Indicates the last transfer of a memory access. DMAReq0:3 are used by slave peripherals to indicate they are prepared to transfer data. DMAAck0:3 are used by the PPC405CR to indicate that data transfers have occurred. End Of Transfer/Terminal Count. I/O O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
7
PerCS1:7[GPIO10:16]
O[I/O]
1, 7
PerOE
O
5V tolerant 3.3V LVTTL
7
PerR/W
I/O
5V tolerant 3.3V LVTTL
1
PerReady PerBLast DMAReq0:3 DMAAck0:3 EOT0:3/TC0:3
I I/O I O I/O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1 1, 7 1 6 1
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Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See "External Bus Control Signals" on page 22.
Signal Name Description I/O Type
Notes
External Master Peripheral Interface
PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Peripheral clock to be used by an external master and by synchronous peripheral slaves. Peripheral reset to be used by an external master and by synchronous peripheral slaves. Hold Request, used by an external master to request ownership of the peripheral bus. Hold Acknowledge, used by the PPC405CR to transfer ownership of peripheral bus to an external master. ExtReq is used by an external master to indicate it is prepared to transfer data. ExtAck is used by the PPC405CR to indicate a data transfer cycle. Used by an external master to indicate the priority of a given external master tenure. Used when the PPC405CR needs to regain control of the peripheral interface from an external master. Used as an input to indicate that an external slave peripheral error has occurred. O O I O I O I O I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 5 1, 5 6 1 6 1
Internal Peripheral Interface
UARTSerClk Serial clock. Used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either UART. UART0 Receive (serial data in). UART0 Transmit (serial data out). UART0 Data Carrier Detect. UART0 Data Set Ready. UART0 Clear To Send. UART0 Data Terminal Ready. UART0 Request To Send. UART0 Ring Indicator. UART1 Receive (serial data in). I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI UART1_Rx
I O I I I O O I I
1 6 1 1 1 6 6 1 1
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Table 6. Signal Functional Description (Sheet 4 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See "External Bus Control Signals" on page 22.
Signal Name UART1_Tx Description UART1 Transmit (serial data out). UART1 Data Set Ready or UART1 Clear To Send. To access this function, software must toggle a DCR register bit. UART1 Request To Send or UART1 Data Terminal Ready. To access this function, software must toggle a DCR register bit. IIC serial clock. IIC serial data. I/O O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
6
UART1_DSR/ [UART1_CTS]
I
1
UART1_RTS/ [UART1_DTR]
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
6
IICSCL IICSDA
I/O I/O
1, 2 1, 2
Interrupts Interface
IRQ0:6[GPIO17:23] Interrupt requests or General Purpose I/O. To access this function, software must toggle a DCR register bit. I[I/O] 5V tolerant 3.3V LVTTL 1
JTAG Interface
TDI TMS TDO TCK TRST Test data in. JTAG test mode select. Test data out. JTAG test clock. The frequency of this input can range from DC to 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405CR. I I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 5 1, 4 1, 4
System Interface
SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an open-drain output (two states, 0 or open circuit). Set to 1 when a Machine Check is generated. Halt from external debugger. I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 2 1, 2
SysReset
I/O
SysErr Halt
O I
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Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 21 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull-up or pull-down required. 7. Pull-up may be required. See "External Bus Control Signals" on page 22.
Signal Name GPIO1[TS1E] GPIO2[TS2E] Description General Purpose I/O or Even Trace execution status. To access this function, software must toggle a DCR register bit. General Purpose I/O or Odd Trace execution status. To access this function, software must toggle a DCR register bit. General Purpose I/O GPIO5:8[TS3:6] Trace status. To access this function, software must toggle a DCR register bit. General Purpose I/O or Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR register bit. Test Enable. Receiver Inhibit. Used only for manufacturing tests. Pull up for normal operation. Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up for normal operation. An external clock input than can be used as an alternative to SysClk to run the CPU core. Which clock input is used is determined by software settings. I/O[O] 5V tolerant 3.3V LVTTL 1 I/O Type 5V tolerant 3.3V LVTTL
Notes
I/O[O]
1, 6
GPIO3[TS1O] GPIO4[TS2O]
I/O[O]
5V tolerant 3.3V LVTTL
1, 6
GPIO9[TrcClk]
I/O[O]
5V tolerant 3.3V LVTTL
1
TestEn RcvrInh DrvrInh1:2 TmrClk
I I I I
2.5V CMOS w/pull-down 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 2 2 1
Power
GND AVDD OVDD VDD Ground Note: Pins J9-J12, K9-K12, L9-L12, and M9-M12 are also thermal balls. Filtered voltage input for PLL (analog) circuits Output driver voltage--3.3V Logic voltage--2.5V
Other pins
Reserved Connect G19 to GND. Do not connect signals, voltage, or ground to any other reserved pins.
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Data Sheet
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) PLL Supply Voltage Input Voltage (2.5V CMOS receivers) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Note: All specified voltages are with respect to GND. Symbol VDD OVDD AVDD VIN VIN VIN TSTG TC Value 0 to +2.7 0 to +3.6 0 to +2.7 -0.6 to VDD+0.6 -0.6 to OVDD+0.6 -0.6 to OVDD+2.4 -55 to +150 -40 to +120 Unit V V V V V V C C
Figure 3. Package Thermal Specifications
The PPC405CR is designed to operate within a case temperature range of -40C to +85C. Thermal resistance values for the EPBGA package in a convection environment are as follows:
Thermal Resistance
Junction-to-case Case-to-ambient Notes:
1
Symbol 0 (0)
Airflow ft/min (m/sec)
100 (0.51) 2 16 200 (1.02) 2 15 2 18
Unit
C/W C/W
JC CA
1. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax - PxJC, where TJMax is maximum junction temperature and P is power consumption.
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Data Sheet
Table 8. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Parameter Logic Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Logic High (2.5V CMOS receivers) Input Logic High (3.3V LVTTL receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Low (2.5V CMOS receivers) Input Logic Low (3.3/5.0V LVTTL receivers) Output Logic High Output Logic Low 3.3V I/O Input Current (no pull-up or pull-down) Input Current (with internal pull-down) 5V Tolerant I/O Input Current 1 Input Max Allowable Overshoot (2.5V CMOS receivers) Input Max Allowable Overshoot (3.3V LVTTL receivers) Input Max Allowable Overshoot (5.0V LVTTL receivers) Input Max Allowable Undershoot Output Max Allowable Overshoot Output Max Allowable Undershoot Case Temperature Notes: 1. See "5V-Tolerant I/O Input Current" on page 30 Symbol VDD OVDD AVDD VIH VIH VIH VIL VIL VOH VOL IIL1 IIL2 IIL4 VIMAO25 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 TC -0.6 -40 +85 -0.6 OVDD + 0.3 10 (@ 0V) 10 Minimum +2.3 +3.0 +2.3 +1.7 +2.0 +2.0 0 0 +2.4 0 Typical +2.5 +3.3 +2.5 Maximum +2.7 +3.6 +2.7 VDD OVDD +5.0 +0.7 +0.8 OVDD +0.4 10 +400 (@ VDD) -650 VDD + 0.6 OVDD + 0.6 +5.5 Unit V V V V V V V V V V Notes
A A A
V V V V V V C
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Data Sheet
Figure 4. 5V-Tolerant I/O Input Current
100 0 -100 Input Current (A) -200 -300 -400 -500 -600 -700 0.0
1.0
2.0
3.0
4.0
5.0
Input Voltage (V)
Table 9. Input Capacitance
Parameter 3.3V LVTTL I/O 5V tolerant LVTTL I/O RX only pins Symbol CIN1 CIN2 CIN4 Maximum 5.4 4.4 3.4 Unit pF pF pF Notes
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 10. DC Electrical Characteristics
Parameter Active Operating Current (VDD)--133MHz Active Operating Current (OVDD)--133MHz Active Operating Current (VDD)--200MHz Active Operating Current (OVDD)--200MHz Active Operating Current (VDD)--266MHz Active Operating Current (OVDD)--266MHz PLL VDD Input current Note: 1. Maximum power is characterized at VDD = 2.7V, OVDD = 3.6V, TC = 85C, across the silicon process (worse case to best case), while running an application designed to maximize power consumption. The specification at 200MHz corresponds to CPU = 200 MHz, PLB = 100MHz, OPB = EBC = 50MHz. The 266MHz maximum power was measured with CPU = 266.6MHz, PLB =133.3MHz, OPB = EBC = 66.6MHz. 2. AVDD should be derived from VDD using the following circuit: Symbol IDD IODD IDD IODD IDD IODD IPLL Minimum Typical TBD TBD 400 35 TBD TBD 16 Maximum TBD TBD 610 40 TBD TBD 23 Unit mA mA mA mA mA mA mA
VDD L1
AVDD
+ C1 C2 C3
AGND GND
L1 - 2.2H SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S) C1 - 3.3 F SMT tantalum C2 - 0.1F SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 - 0.01 F SMT monolithic ceramic capacitor with X7R dielectric or equivalent
Test Conditions
Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." AC specifications are characterized at OVDD = 3 V and TJ = +85C with the 50pF test load shown in the figure at right.
Output Pin 50pF
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PPC405CR - PowerPC 405CR Embedded Processor
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Data Sheet
Table 11. Clocking Specifications
Symbol CPU PFC PTC SysClk Input SCFC SCTC SCTCS SCTCH SCTCL Clock input frequency Clock period Clock edge stability (phase jitter, cycle to cycle) Clock input high time Clock input low time 40% of nominal period 40% of nominal period 25 15 66.66 40 0.15 60% of nominal period 60% of nominal period MHz ns ns ns ns Processor clock frequency Processor clock period 133.33/200/266.66 7.5/5/3.75 MHz ns Parameter Min Max Units
Note: Input slew rate > 2V/ns MemClkOut Output MCOFC MCOTC MCOFC MCOTC MCOFC MCOTC MCOTCS MCOTCH MCOTCL Other Clocks VCOFC PLBFC PLBFC PLBFC OPBFC OPBFC OPBFC VCO frequency PLB frequency @ PFC = 133MHz PLB frequency @ PFC = 200MHz PLB frequency @ PFC = 266MHz OPB frequency @ PFC = 133MHz OPB frequency @ PFC = 200MHz OPB frequency @ PFC = 266MHz 400 800 66.66 100 133.33 33.33 50 66.66 MHz MHz MHz MHz MHz MHz MHz Clock output frequency @ PFC = 133MHz Clock period @ PFC = 133MHz Clock output frequency @ PFC = 200MHz Clock period @ PFC = 200MHz Clock output frequency @ PFC = 266MHz Clock period @ PFC = 266MHz Clock edge stability (phase jitter, cycle to cycle) Clock output high time Clock output low time 45% of nominal period 45% of nominal period 7.5 0.2 55% of nominal period 55% of nominal period 10 133.33 15 100 66.66 MHz ns MHz ns MHz ns ns ns ns
Figure 5. Timing Waveform
2.0V 1.5V 0.8V TCH TC TCL
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405CR. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405CR the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405CR with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405CR peripherals impose more stringent requirements (see Note 1). Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. Use the SDRAM MemClkOut since it also tracks the modulation.
* * * Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation. 2. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the PPC405CR meets the above requirements and does not adversely affect other aspects of the system.
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 12. Peripheral Interface Clock Timings
Parameter PerClk output frequency--133MHz PerClk period--133MHz PerClk output frequency--200MHz PerClk period--200MHz PerClk output frequency--266MHz PerClk period--266MHz PerClk output high time PerClk output low time PerClk clock edge stability (phase jitter, cycle to cycle) UARTSerClk input frequency (Note 1) UARTSerClk period UARTSerClk input high time UARTSerClk input low time TmrClk input frequency--133MHz TmrClk period--133MHz TmrClk input frequency--200MHz TmrClk period--200MHz TmrClk input frequency--266MHz TmrClk period--266MHz TmrClk input high time TmrClk input low time Notes: 1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock frequency is 50MHz for 200MHz parts and 66.66MHz.for 266MHz parts. - 2TOPB+2 TOPB+1 TOPB+1 - 30 - 20 - 15 40% of nominal period 40% of nominal period Min - 30 - 20 - 15 45% of nominal period 45% of nominal period Max 33.33 - 50 - 66.66 - 55% of nominal period 55% of nominal period 0.3 1000/(2TOPB+2ns) - - - 33.33 - 50 - 66.66 - 60% of nominal period 60% of nominal period Units MHz ns MHz ns MHz ns ns ns ns MHz ns ns ns MHz ns MHz ns MHz ns ns ns
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AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Figure 6. Input Setup and Hold Waveform
Clock
TIS min Inputs Valid
TIH min
Figure 7. Output Delay and Float Timing Waveform
Clock
TOV max Outputs TOH min
TOV max TOH min
TOV max TOH min
High (Drive) Float (High-Z) Low (Drive) Valid Valid
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing value of na means "not applicable" and dc means "don't care." 2. See "Test Conditions" on page 31 for output capacitive loading. 3. I/O H is specified at 2.4V; I/O L is specified at 0.4V Table 13. I/O Specifications--All speeds
Input (ns) Signal Setup Time (TIS min) n/a n/a n/a n/a n/a n/a n/a Hold Time (TIH min) n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Output (ns) Valid Delay (TOV max) n/a n/a Hold Time (TOH min) n/a n/a Output Current (mA) I/O H (min) 19 19 12 12 12 12 12 12 12 12 12 n/a n/a 12 n/a 12 n/a n/a 12 n/a n/a dc dc n/a n/a n/a I/O L (min) 12 12 8 8 8 8 8 8 8 8 8 n/a n/a 8 n/a 8 n/a n/a 8 n/a n/a n/a async async async async async Clock Notes
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_RTS [UART1_DTR] UART1_DSR [UART1_CTS] UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
IRQ0:6[GPIO17:23] JTAG Interface TCK TDI TDO TMS TRST
System Interface
DrvrInh1:2 GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] Halt RcvrInh SysClk SysErr SysReset TestEn TmrClk dc dc dc dc dc dc dc dc n/a n/a n/a n/a 10 n/a n/a n/a n/a n/a n/a 1 n/a n/a
12
8
n/a n/a n/a 12 12 n/a n/a
n/a n/a n/a 8 8 n/a n/a
async
async async async async
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 14. I/O Specifications--133 and 200MHz
Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. 5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) n/a n/a n/a n/a n/a n/a 2 n/a 2 n/a n/a n/a dc dc 4 4 n/a 6 n/a 4 5 9 4 n/a n/a 6 n/a n/a 4 6 n/a 4 Hold Time (TIH min) n/a n/a n/a n/a n/a n/a 1 n/a 1 n/a n/a n/a dc dc 1 1 n/a 1 n/a 1 1 1 1 n/a n/a 1 n/a n/a 1 1 n/a 1 Output (ns) Valid Delay (TOV max) 7.3 5.8 7.3 4.7 6.2 6 6 7.8 6.2 7.4 7.4 8 n/a 9 10 8 9 10 8 10.5 8 n/a 8 8 8 n/a 8 8 n/a n/a 0.9 n/a Hold Time (TOH min) 1 1 1 1 1 1 1 1 1 1 1 0 n/a 0 0 0 0 0 0 0 0 n/a 0 0 0 n/a 0 0 n/a n/a 0.9 n/a Output Current (mA) I/O H (min) 19 19 19 40 19 19 19 19 19 19 19 12 n/a 12 19 12 12 19 12 19 12 n/a 12 12 12 n/a 19 12 n/a n/a 19 n/a I/O L (min) 12 12 12 25 12 12 12 12 12 12 12 8 n/a 8 12 8 8 12 8 12 8 n/a 8 8 8 n/a 12 8 n/a n/a 12 n/a Clock Notes
SDRAM Interface
BA1:0 BankSel0:3 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 4 1, 2 2 1, 2 2 2 2 2 1, 2 2 1, 2 1, 2
External Slave Peripheral Interface
External Master Peripheral Interface
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 15. I/O Specifications--266MHz
Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. 5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) n/a n/a n/a n/a n/a n/a 1.5 n/a 1.5 n/a n/a n/a dc dc 3 3.5 n/a 5 n/a 3.5 4 6.5 3 n/a n/a 5 n/a n/a 3 5 n/a 3 Hold Time (TIH min) n/a n/a n/a n/a n/a n/a 1 n/a 1 n/a n/a n/a dc dc 1 1 n/a 1 n/a 1 1 1 1 n/a n/a 1 n/a n/a 1 1 n/a 1 Output (ns) Valid Delay (TOV max) 5.5 4.5 5.5 3.9 4.9 4.7 4.7 5.9 4.8 5.6 5.6 6 n/a 8 8 6 6 8 6 8 6 n/a 6 6 6 n/a 6 6 n/a n/a 0.9 n/a Hold Time (TOH min) 1 1 1 1 1 1 1 1 1 1 1 0 n/a 0 0 0 0 0 0 0 0 n/a 0 0 0 n/a 0 0 n/a n/a 0.9 n/a Output Current (mA) I/O H (min) 19 19 19 40 19 19 19 19 19 19 19 12 n/a 12 19 12 12 19 12 19 12 n/a 12 12 12 n/a 19 12 n/a n/a 19 n/a I/O L (min) 12 12 12 25 12 12 12 12 12 12 12 8 n/a 8 12 8 8 12 8 12 8 n/a 8 8 8 n/a 12 8 n/a n/a 12 n/a Clock Notes
SDRAM Interface
BA1:0 BankSel0:3 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 4 1, 2 2 1, 2 2 2 2 2 1, 2 2 1, 2 1, 2
External Slave Peripheral Interface
External Master Peripheral Interface
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AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405CR start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V or 10k to +5V. The recommended pull-down is 1K to GND. These pins are use for strap functions only during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options. The signal names assigned to the pins for normal operation follow the pin number. Table 16. Strapping Pin Assignments (Sheet 1 of 2)
Function PLL Tuning
1
Option W15 UART0_Tx Choice 1; TUNE[5:0] = 010001 Choice 2; TUNE[5:0] = 010010 Choice 3; TUNE[5:0] = 010011 Choice 4; TUNE[5:0] = 010100 Choice 5; TUNE[5:0] = 010101 Choice 6; TUNE[5:0] = 010110 Choice 7; TUNE[5:0] = 010111 Choice 8; TUNE[5:0] = 100100 0 0 0 0 1 1 1 1 C16 DMAAck0 Bypass mode Divide by 3 Divide by 4 Divide by 6 0 0 1 1 B16 DMAAck2 Divide by 1 Divide by 2 Divide by 3 Divide by 4 0 0 1 1 B18 GPIO1[TS1E] Divide by 1 Divide by 2 Divide by 3 Divide by 4 0 0 1 1 T4 HoldAck Divide by 1 Divide by 2 Divide by 3 Divide by 4 0 0 1 1
Ball Strapping U13 UART0_DTR 0 0 1 1 0 0 1 1 B17 DMAAck1 0 1 0 1 A14 DMAAck3 0 1 0 1 D16 GPIO2[TS2E] 0 1 0 1 U5 ExtAck 0 1 0 1 V20 UART0_RTS 0 1 0 1 0 1 0 1
for 6 M 7 use choice 3 for 7 < M 12 use choice 5 for 12 < M 32 use choice 6 See Note.
PLL Forward Divider
2
PLL Feedback Divider
2
PLB Divider from
CPU2, 3
OPB Divider from
PLB2
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Table 16. Strapping Pin Assignments (Sheet 2 of 2)
Function External Bus Divider from PLB
2, 3
Option C17 GPIO3[TS1O] Divide by 2 Divide by 3 Divide by 4 Divide by 5 0 0 1 1 Y5 UART1_Tx 8-bit ROM 16-bit ROM 32-bit ROM Reserved 0 0 1 1
Ball Strapping P18 GPIO4[TS2O] 0 1 0 1 W6 UART1_RTS/ UART1_DTR 0 1 0 1
ROM Width
Note: 1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405CR. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405CR, visit the technical documents area of the AMCC PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in "Clocking Specifications" on page 32. Further requirements are detailed in the Clocking chapter of the PowerPC 405CR Embedded Processor User's Manual. 3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
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AMCC
PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Document Revision History
Revision Date Description
1.01 1.02
08/05/04 01/11/05
Initial release Add lead-free part numbers.
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PPC405CR - PowerPC 405CR Embedded Processor
Revision 1.02 - January 11, 2005
Data Sheet
Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 -- (800) 755-2622 -- Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC's Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright (c) 2005 Applied Micro Circuits Corporation.
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